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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
BCD Rate Multiplier
The MC14527B BCD rate multiplier (DRM) provides an output pulse rate based upon the BCD input number. For example, if 6 is the BCD input number, there will be six output pulses for every ten input pulses. This part may be used for arithmetic operations including multiplication and division. Typical applications include digital filters, motor speed control and frequency synthesizers. * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Output Clocked on the Negative Going Edge of Clock * Strobe for Inhibiting or Enabling Outputs * Enable and Cascade Inputs for Cascade Operation of Two or More DRMs * "9" Output for the Parallel Enable Configuration and DRMs in Cascade * Complementary Outputs * Clear and Set to Nine Inputs MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage Value Unit V V
MC14527B
L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
DW SUFFIX SOIC CASE 751G
IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I I III IIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIII
- 0.5 to + 18.0 10 500 Vin, Vout Iin, Iout PD Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW Tstg - 65 to + 150
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
_C
BLOCK DIAGRAM
4 12 RATE INPUT 11 9 10 14 MULTIPLIER 15 2 3 13 VDD = PIN 16 VSS = PIN 8 S Eout CASC Ein CLOCK OUT ST A OUT B C "9" D CLEAR 7 6 5 1
TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
TRUTH TABLE (X = Don't Care, *D = Most Significant Bit)
Output Logic Level Inputs No. of Clock Pulses 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Number of Pulses
D* 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X 1 0 X
C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X X X
B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X X X X
A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X
Ein 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Strobe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Cascade 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Clear 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Out 0 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 -- 0 1 10 0 0
Out 1 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 -- 1 0 10 1 1
Eout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- 1 1 1 1 0
"9" 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- 1 1 0 0 1
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14527B 1
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (0.85 A/kHz) f + IDD IT = (1.75 A/kHz) f + IDD IT = (2.60 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.0012. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
PIN ASSIGNMENT
"9" C D S OUT OUT Eout VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD B A CLEAR CASC Ein ST CLOCK
MC14527B 2
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol tTLH, tTHL VDD 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns Propagation Delay Time Clock to Out tPLH, tPHL = (1.7 ns/pF) CL + 115 ns tPLH, tPHL = (0.66 ns/pF) CL + 67 ns tPLH, tPHL = (0.5 ns/pF) CL + 45 ns Clock to Out tPLH, tPHL = (1.7 ns/pF) CL + 40 ns tPLH, tPHL = (0.66 ns/pF) CL + 32 ns tPLH, tPHL = (0.5 ns/pF) CL + 20 ns Clock to Eout tPLH, tPHL = (1.7 ns/pF) CL + 210 ns tPLH, tPHL = (0.66 ns/pF) CL + 97 ns tPLH, tPHL = (0.5 ns/pF) CL + 60 ns Clock to "9" tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 122 ns tPLH, tPHL = (0.5 ns/pF) CL + 85 ns Set or Clear to Out tPHL = (1.7 ns/pF) CL + 295 ns tPHL = (0.66 ns/pF) CL + 132 ns tPHL = (0.5 ns/pF) CL + 85 ns Cascade to Out tPHL = (1.7 ns/pF) CL + 40 ns tPHL = (0.66 ns/pF) CL + 32 ns tPHL = (0.5 ns/pF) CL + 20 ns Strobe to Out tPHL = (1.7 ns/pF) CL + 145 ns tPHL = (0.66 ns/pF) CL + 72 ns tPHL = (0.5 ns/pF) CL + 45 ns Clock Pulse Width tPHL, tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 tPLH 5.0 10 15 tPLH 5.0 10 15 tWH 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- 500 200 150 -- -- -- -- -- -- 240 100 75 0 0 0 400 150 120 230 105 70 250 110 80 2.0 4.5 6.0 -- -- -- 80 35 30 - 20 - 10 - 7.5 175 60 45 260 210 140 -- -- -- 1.2 2.5 3.5 15 5 4 -- -- -- -- -- -- -- -- -- ns -- -- -- 125 65 45 250 130 90 ns -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 200 100 70 125 65 45 295 130 85 400 155 110 380 165 110 400 200 140 ns 250 130 90 ns 590 260 170 ns 800 310 220 ns 760 330 220 ns ns tPLH. tPHL tPLH, tPHL tPHL Clock Pulse Frequency fcl MHz Clock Pulse Rise and Fall Time tTLH, tTHL tWH s Set or Clear Pulse Width ns Set Removal Time trem ns Enable In Setup Time tsu ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
MOTOROLA CMOS LOGIC DATA
MC14527B 3
012345678901234 CLOCK VDD Qa Qb S CASC Eout Ein CLOCK OUT ST A OUT B C "9" D CLEAR VSS Qc Qd R1 R2 R3 R4 OUTPUT (PIN 6) A ENABLED B ENABLED C ENABLED D ENABLED
PULSE GENERATOR MULTIPLIER PRESET NO.
Figure 1. Test Circuit and Timing Diagram
Eout OUTPUT (PIN 6) (PRESET NO. OF 1) (PRESET NO. OF 2) (PRESET NO. OF 3) VDD S CASC Ein CLOCK ST A B C D CLEAR Eout OUT OUT CL "9" VSS CL CL CL (PRESET NO. OF 4) (PRESET NO. OF 5) (PRESET NO. OF 6) (PRESET NO. OF 7) (PRESET NO. OF 8) (PRESET NO. OF 9)
PROGRAMMABLE PULSE GENERATOR
20 ns tTLH CLOCK SET
20 ns tTHL 50%
1 fcl
90% 10%
trem ENABLE IN SET 50% tsu tWH 50% tPHL OUT tPLH 50% tPHL tTLH 90% 10% tTHL
Figure 2. Switching Time Test Circuit and Waveforms
MC14527B 4
MOTOROLA CMOS LOGIC DATA
VDD 0.01 F CERAMIC
ID VDD S CASC Eout Ein CLOCK OUT ST A OUT B C D "9" CLEAR VSS
500 pF
PULSE GENERATOR
20 ns CLOCK CL CL CL CL 90% 50% 10% VARIABLE WIDTH 50% DUTY CYCLE
20 ns VDD VSS
Figure 3. Power Dissipation Test Circuit and Waveform
LOGIC DIAGRAM
ENABLE IN 11 DC BA 2 15 14 STROBE CASCADE 10 12
3
T Ca R
Q Q R1 6 OUT
CLOCK
9
T Cb R
R2 Q 5 OUT R3 R4
T
S
Q Q
VDD = PIN 16 VSS = PIN 8
Cc R
TSQ Cd R Q
1 "9"
7 ENABLE OUT CLEAR 13 SET TO NINE 4
MOTOROLA CMOS LOGIC DATA
MC14527B 5
MOST SIGNIFICANT DIGIT 1 0 0 1 A OUT B C 1 D Eout CLOCK CASC Ein "9" ST CLEAR S 0 0 1 0
LEAST SIGNIFICANT DIGIT A OUT B C 2 D Eout CLOCK CASC Ein "9" ST CLEAR S
NOTE: More than two MC14527Bs may be cascaded using this configuration.
CLOCK CLOCK OUT DRM 2
0 1 2345 6 78 9012 34 5678 90
One of four output pulses contributed by DRM 2 to output for every 100 clock pulses in for preset No. of 94.
Figure 4. Two MC14527Bs in Cascade with Preset No. of 94
MC14527B 6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MOTOROLA CMOS LOGIC DATA
MC14527B 7
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 _ C -T-
14X DIM A B C D F G J K M P R
G
K
SEATING PLANE
M
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MC14527B 8
*MC14527B/D*
MOTOROLA CMOS LOGIC DATA MC14527B/D

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